A Merged Memory Logic (MML) device, which has recently appeared in applications, is a device including a Dynamic Random Access Memory (DRAM) and peripheral circuits integrated on a single chip.
By virtue of the appearance of such an MML, functions of multimedia are significantly improved, and high-integration and high-speed operation of a semiconductor device can be effectively achieved. Meanwhile, for analog circuits requiring high-speed operation, semiconductor devices for realizing a mass storage capacitor are being developed. In general, where a capacitor has a Polysilicon-Insulator-Polysilicon (PIP) structure, the top electrode and the bottom electrode include conductive polysilicon. Because the top/bottom electrodes are formed from polysilicon, the capacitance decreases because of the natural oxide layers that form due to an oxidation reaction occurring at the interfacial surface between the top/bottom electrodes and a dielectric thin film.
Further, due to a depletion region formed in a polysilicon layer, the capacitor of the PIP structure has another disadvantage in that the capacitance decreases and becomes unsuitable for high-speed and high-frequency operation.
In order to solve the above problems, there has been proposed a capacitor having a Metal-Insulator-Silicon (MIS) structure or a Metal-Insulator-Metal (MIM) structure.
Among other things, the MIM type capacitor has been mainly used for high performance semiconductor devices because it has low resistivity and does not cause parasitic capacitance derived from the depletion.
Recently, various technologies have been developed to provide a metal interconnection of a semiconductor device using copper, which has specific resistance lower than that of aluminum. Thus, various capacitors having the MIM structure employing copper electrodes have been suggested.
FIGS. 1A and 1B are cross-sectional views for illustrating a conventional fabricating method of a semiconductor device having a damascene interconnection structure.
Referring to FIG. 1A, a first metallic interconnection 15 and a second metallic interconnection 20 are formed on a bottom insulating layer 10 of a semiconductor substrate 1 in such a manner that the first and second metallic interconnections 15 and 20 do not form a step difference relative to the bottom insulating layer 10. After forming a metallic layer on the substrate including the first metallic interconnection 15 and the second metallic interconnection 20, the metallic layer is patterned to form a bottom electrode 25 of a capacitor on a top surface of the second metallic interconnection 20. Then, a dielectric layer 30 is formed on the bottom electrode 25. After that, another metallic layer is formed on the dielectric layer 30 and patterned to form a top electrode 35 of the capacitor on the bottom electrode 25. An interlayer dielectric layer 40 is then formed on the resultant structure including the top electrode 35.
Next, referring to FIG. 1B, a top surface of the interlayer dielectric layer 40 is planarized by a CMP process. Then, the interlayer dielectric layer 40 and the dielectric layer 30 are etched to form a via hole V1 for exposing a top surface of the first metallic interconnection 15. A first trench T1 is formed above the via hole V1 and a second trench T2 for exposing a top surface of the top electrode 35 is formed. Thereafter, the via hole V1 and the first and second trenches T1 and T2 are filled with Cu and then a CMP process is performed with respect to the Cu, thereby forming a damascene interconnection structure 45 and a contac plug 50.
However, such a convectional technique has problems as follws. A metallic Interconection process for applying a bias voltage to the bottom electrode of the capacitor must be additionally carried out, and the process becomes complex because the via hole V1 and the trench of the top electrode 35 cannot be simultaneously formed.
Meanwhile, as the capacitor plays a great role in the structure of a logic device, there is a technical need to improve the capacitance of the capacitor.
There are several methods for maintaining the capacitance of a capacitor in an appropriate value in a limited unit area, as seen from the relationship C=∈As/d (∈: dielectric constant, As: surface area of electrode, d: thickness of dielectric element). That is, there has been suggested methods for maintaining a desired capacitance, including: a method for reducing the thickness of the dielectric element, a method of increasing the surface area of the electrode, and a method of using a material having a high dielectric constant ∈. When considering the method of increasing the surface area of the electrode, since the conventional analog capacitor employs a metallic interconnection as top and bottom electrodes, the effective surface area of the conventional analog capacitor is formed as a plane. Therefore, the surface area of an electrode is physically limited.
FIGS. 2A to 2E are cross-sectional views for illustrating a conventional fabricating method of a semiconductor device having a capacitor and a contact plug between interlayer interconnections.
Referring to FIG. 2A, an interlayer dielectric layer 2 is formed, and a metallic conductive layer is formed and patterned on the interlayer dielectric layer 2 such that a bottom electrode 4a and a bottom interconnection 4b are formed.
Although not shown in the figures, a semiconductor substrate, on which the semiconductor device is formed, exists under the interlayer dielectric layer 2.
An inter-metallic dielectric layer 6 is formed on the bottom electrode 4a and the bottom interconnection 4b, and then planarized.
Referring to FIG. 2B, a contact hole 8 for exposing the bottom electrode 4a of the capacitor is formed using a conventional photolithographic process. The contact hole 8 exposing the bottom electrode may constitute an effective surface area of the capacitor, so the capacitor has a large effective surface area.
Referring to FIG. 2C, a dielectric layer 10 is formed on an entire surface of the substrate including the contact hole 8.
Referring to FIG. 2D, a via hole 12 for exposing the bottom interconnection 4b is formed using a conventional photolithographic process. After that, referring to FIG. 2E, a top interconnection conductive layer is formed and patterned on an entire surface of the semiconductor substrate, thereby forming a top electrode 14a and a top interconnection 14b of the capacitor.
However, the conventional MIM capacitor described above is limited in its ability to increase the capacitance of the capacitor because the effective surface area of the capacitor is formed as a plane.